Programmable General Purpose Embedded Controller 128-Pin LQFP T/R

The MEC1310 is a 128-pin 3.3V LPC-based ACPI 2.0and PC99/PC2001 compliant Notebook I/O Controller. The MEC1310 incorporates a high-performance 8051-based keyboard and system controller with internal embedded 64K SRAM; a 1K byte Boot ROM, and 64- bytes battery backed registers. The embedded 64K SRAM is loaded via HOST/8051 SPI Memory Inter- face. The HOST/8051 SPI Memory Interface can be configured in Switched SPI Flash Configuration or Par- allel Shared SPI Flash Configuration. The MEC1310 has four PS/2 ports; an 16C550A-com- patible 2 pin UART for Debug Port; three 8584-style I2C/SMBus controllers with two selectable ports per controller; a Serial IRQ peripheral agent interface; three ACPI Embedded Controller Interface; General Purpose I/O pins and seven General Purpose Outputs; four independently programmable pulse width modula- tors; dual fan control through the implementation of two fan tachometer input pins, RPM-PWM block with one tachometer input and one PWM output; hardware mon- itoring of a PWM input and maskable hardware wake- up events; one BC-Link Combined High Speed/Low Speed Bus Master Controller; 5 channel Analog to Dig- ital Converter. The MEC1310 has two separate power planes to pro- vide “instant on” and system power management func- tions. Additionally, the MEC1310 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. Wake-up events and ACPI-related functions are supported through the SCI Interface. The MEC1310 supports the ISA Plug-and-Play Stan- dard (Version 1.0a) and provides all the functionality for current Windows O/S’s. The I/O Address and Hard- ware IRQ of each logical device in the MEC1310 may be reprogrammed through the internal configuration registers. There are 480 I/O address location options and 15 IRQs for each logical device.

• 3.3V Operation with 5V Tolerant Buffers on PS/2pins
• ACPI 1.0/2.0 PC99/PC2001 Compliant
• LPC Interface with Clock Run Support
  • Supports LPC Bus frequencies of 19.2MHz to33MHz
  • Serial IRQ Interface Compatible with Serial-ized IRQ Support for PCI Systems
  • 15 Direct IRQs
  • ACPI SCI Interface
  • nSMI output and supporting PM registers
  • Shadowed write only registers
• Internal 64K SRAM in MEC1310
  • Loaded at VCC1 power from the HOST/8051SPI Memory Interface
  • Provides 64KB of 8051 program space
  • 32k-Byte region shared with 8051data space
• HOST/8051 SPI Memory Interface
  • 3-pin Full Duplex serial communication inter-face.
  • One Chip Select Pins
  • Fully 8051 Controlled
  • Hardware Support for two SPI Flash Configu-rations: Switched SPI Flash Configuration Parallel Shared SPI Flash Configuration Debug Programming Interface
• Two Power Planes
  • Low Standby Current in Sleep Mode
• Three ACPI Embedded Controller Interface
• Configuration Register Set Compatible with ISAPlug-and-Play Standard (Version 1.0a)
• High-Performance Embedded 8051 Keyboard and System Controller
  • Provides System Power Management
  • System Watch Dog Timer (WDT)
  • 8042 Style Host Interface
  • Supports Interrupt and Polling Access
  • 1024 Boot /ROM
  • 256 Bytes Data RAM
  • On-Chip Memory-Mapped Control Registers
  • Access to VCC0 Backed Registers
  • Up to 18x8 Keyboard Scan Matrix
  • Two 16-Bit Timer/Counters
  • Integrated Full-Duplex Serial Port Interface
  • Seventy-Three 8051 Interrupt Sources
  • Thirty-Two 8-Bit, Host/8051 Mailbox Regis-ters
  • Sixty-Four Maskable Hardware Wake-Up Events
  • Fast GATEA20
  • Fast CPU_RESET
  • Multiple Clock Sources and Operating Fre-quencies
  • IDLE and SLEEP Modes
  • Trace FIFO Debug Port
• Accurate Fail-Safe Ring Oscillator
  • Single Clock source for most 8051 and SIOfunctions
  • Provides 2% frequency accuracy
  • Lock Bit provides status
  • 32.768KHz-input clock Single ended input Compatible with south bridge SUSCLK/RSMRST# gating rules replacement 32K distribution available when RSMRST# is asserted Very low power state with only external 32K clock distributed
• Integrated Standby Power Reset Generator
  • VCC1_RST# open drain output
  • Accepts External driven Reset
• VCC0 Backed Resources
  • 64 Byte VCC0 Backed Registers
  • VCC0 Backed Status Register
• Three 8584-Style I2C/SMBus Controllers
  • 8051 Controlled Logic Allows I2C/SMBus Master or Slave Operation
  • I2C/SMBus Controllers are Fully Operational on Standby Power
  • Two Controllers with 2 Sets of Dedicated Pins per I2C/SMBus Controller
  • One Controller with one Set of Dedicated Pins per I2C/SMBus Controller
• Four independent Hardware Driven PS/2 Ports
  • GPIO signal function associated with each pin
• PECI Interface 2.0
• 56 General Purpose I/O Pins
  • Maskable Hardware Wake-Event Capable
  • Programmable Open-Drain/Push-Pull Out-puts
• 7 General-Purpose Outputs
• Four Programmable Pulse-Width Modulator Out-puts
  • Independent Clock Rates
  • 6-Bit Duty Cycle Granularity
  • Operational in both Full on and Standby modes
• Dual Fan Tachometer Inputs
• RPM-Based Fan Speed Control Algorithm
  • Utilizes one TACH input and one PWM output
  • 3% accurate from 500 RPM to 16k RPM
  • Ramp Rate Control RPM-based Fan Speed Control Algorithm