HyperRAM Self-Refresh DRAM

The Cypress 64-Mbit HyperRAMTM device is a high-speed CMOS, self-refresh Dynamic RAM (DRAM), with a HyperBus interface. The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM (PSRAM). 3.0V I/O, 11 bus signals – Single ended clock (CK) ? 1.8V I/O, 12 bus signals – Differential clock (CK, CK#) ? Chip Select (CS#) ? 8-bit data bus (DQ[7:0]) ? Read-Write Data Strobe (RWDS) – Bidirectional Data Strobe / Mask – Output at the start of all transactions to indicate refresh latency – Output during read transactions as Read Data Strobe – Input during write transactions as Write Data Mask ? RWDS DCARS Timing – During read transactions RWDS is offset by a second clock, phase shifted from CK – The Phase Shifted Clock is used to move