Clock Divider

The ICS542 is cost effective way to produce a high-qualityclock output divided from a clock input. The chip accepts aclock input up to 156 MHz at 3.3 V and produces a divide by2, 4, 6, 8, 12, or 16 of the input clock. There are two outputson the chip, one being a low-skew divide by two of the other. For instance, if an 100 MHz input clock is used, the ICS542can produce low-skew 50 MHz and 25 MHz clocks, or lowskew 25 MHz and 12.5 MHz clocks. The chip has anall-chip power-down mode that stops the outputs low, andan OE pin that tri-states the outputs. See the ICS541 and ICS543 for other clock dividers, andthe ICS501, 502, 511, 512, and 525 for clock multipliers.

• 8-pin SOIC package, Pb free
• Available in RoHS compliant package
• IDT’s lowest cost clock divider
• Low skew (500 ps) outputs. One is /2 of the other
• Easy to use with other generators and buffers
• Input clock frequency up to 156 MHz
• Output clock duty cycle of 45/55
• Power-down turns off chip
• Output Enable
• Advanced, low-power CMOS process
• Operating voltage of 3.3 V or 5 V
• Does not degrade phase noise - no PLL
• Available in industrial and commercial temperature ranges