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Found: 5'344
Product SKU Price
LOGICORE, HDCP CONTROLLER, WORLDWIDE LICENSE LOGICORE, HDCP CONTROLLER, WORLDWIDE LICENSE EF-DI-HDCP-WW Submit request
LOGICORE, HDCP CONTROLLER, SITE LICENSE LOGICORE, HDCP CONTROLLER, SITE LICENSE EF-DI-HDCP-SITE Submit request
License For Digital Pre-Distortion Solution License For Digital Pre-Distortion Solution EF-DI-DPD-SITE Submit request
REED SOLOMON ENCODER IMPLEMENTS MANY DIFFERENT REED SOLOMON CODING STANDARDSThe Reed-Solomon Encoder LogiCORE module is a high speedand compact design that implements many different Reed-Solomon coding. REED SOLOMON ENCODER IMPLEMENTS MANY DIFFERENT REED SOLOMON CODING STANDARDSThe Reed-Solomon Encoder LogiCORE module is a high speedand compact design that implements many different Reed-Solomon coding. EF-DI-RSE-SITE Submit request
License For 3GPP LTE Channel Estimator LogiCORE License For 3GPP LTE Channel Estimator LogiCORE EF-DI-CHEST-LTE-SITE Submit request
Logicore IP Is A High-Performance, Low Cost Flexible Solution Logicore IP Is A High-Performance, Low Cost Flexible Solution EF-DI-CPRI-SITE Submit request
LogiCORE IP 10G/25G Ethernet Solution Project License LogiCORE IP 10G/25G Ethernet Solution Project License EF-DI-25GEMAC-PROJ Submit request
The Xilinx Tri-Mode Ethernet MAC core is a parameterizable core ideally suited for use in networking equipment such as switches and routers. The customizable TEMAC core enables system designers to implement a broad range of integrated Ethernet designs. The Xilinx Tri-Mode Ethernet MAC core is a parameterizable core ideally suited for use in networking equipment such as switches and routers. The customizable TEMAC core enables system designers to implement a broad range of integrated Ethernet designs. EF-DI-TEMAC-SITE Submit request
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. EF-DI-PCIX-V5-SITE Submit request
LOGICORE, CANFD FOR AUTOMOTIVE DEVICES (XA), WORLDWIDE LIC LOGICORE, CANFD FOR AUTOMOTIVE DEVICES (XA), WORLDWIDE LIC EF-DI-CANFD-XA-WW Submit request
LOGICORE IP 3GPP LTE MIMO DECODER V1.0 LOGICORE IP 3GPP LTE MIMO DECODER V1.0 EF-DI-MIMODEC-LTE-SITE Submit request
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. EF-DI-PCI32-IP-SITE Submit request
CAN with Flexible Data Rate for Automotive and Industrial Application Site License CAN with Flexible Data Rate for Automotive and Industrial Application Site License EF-DI-CANFD-XA-SITE Submit request
License For Tri-Mode Ethernet Media Access Controller License For Tri-Mode Ethernet Media Access Controller EF-DI-TEMAC-PROJ Submit request
10G/25G Ethernet MAC/PCS + BASE-R Site License 10G/25G Ethernet MAC/PCS + BASE-R Site License EF-DI-25GEMAC-SITE Submit request
CAN with Flexible Data Rate for Non-Automotive Application Site License CAN with Flexible Data Rate for Non-Automotive Application Site License EF-DI-CANFD-XC-SITE Submit request
License For 3GPP LTE RACH Detector License For 3GPP LTE RACH Detector EF-DI-RACH-LTE-SITE Submit request
The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0. The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0. EF-DI-CHDEC-LTE-SITE Submit request
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. EF-DI-PCI32-SP-PROJ Submit request
The USB 2.0 protocol multiplexes many devices over a singleand half-duplex serial bus. The bus runs at 480 Mbps or at 12 Mbps and is designed to be plug-and-play. The USB 2.0 protocol multiplexes many devices over a singleand half-duplex serial bus. The bus runs at 480 Mbps or at 12 Mbps and is designed to be plug-and-play. EF-DI-USB2-DEVICE-SITE Submit request
The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. EF-DI-PCI64-IP-SITE Submit request
The Xilinx Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe) protocol layer core is available for Xilinx low-cost 90nm Spartan-3/3E/3A families. PCIe is a high-speed duplex serial interface standard supported by many industry leaders. The Xilinx Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe) protocol layer core is available for Xilinx low-cost 90nm Spartan-3/3E/3A families. PCIe is a high-speed duplex serial interface standard supported by many industry leaders. EF-DI-PCIE-PIPE-SITE Submit request
License For Serial RapidIO LogiCORE IP License For Serial RapidIO LogiCORE IP EF-DI-RIO-SITE Submit request
License For JESD204 Core LogiCORE IP License For JESD204 Core LogiCORE IP EF-DI-JESD204-SITE Submit request