Erasable Programmable Logic Device 24-Pin CDIP

The Altera Classic device family offers a solution to high-speed, low- power logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version.Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages.EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications.Classic devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly.Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously.

• Complete device family with logic densities of 300 to 900 usable gates
• Device erasure and reprogramming with non Volatile EPROM
• configuration elements
• Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
• as high as 100 MHz
• 24 to 68 pins available in dual in-line package (DIP), plastic J-lead
• chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages
• Programmable security bit for protection of proprietary designs
• 100% generically tested to provide 100% programming yield
• Programmable registers providing D, T, JK, and SR flipflops with
• individual clear and clock controls
• Software design support featuring the Altera development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems
• Programming support with Altera’s Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors
• Additional design entry and simulation support provided by EDIF,
• library of parameterized modules (LPM), Verilog HDL, VHDL, and
• other interfaces to popular EDA tools from manufacturers such as
• Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
• Synplicity, and VeriBest