Zero Delay PLL Clock Buffer Single 52-Pin TQFP

The CY29973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz.

• Output Frequency up to 125 MHz
• 12 Clock Outputs: Frequency Configurable
• 350 ps max. Output to Output Skew
• Configurable Output Disable
• Two Reference Clock Inputs for Dynamic Toggling
• Oscillator or PECL Reference Input
• Spread Spectrum Compatible
• Glitch-free Output Clocks Transitioning
• 3.3 V Power Supply
• Pin Compatible with MPC973
• Industrial Temperature Range: -40 °C to +85 °C
• 52-pin TQFP Package