Zero Delay PLL Clock Buffer Single 40MHz to 140MHz 24-Pin TSSOP

The CY2509 is a PLL-based clock driver designed for use in dual inline memory modules. The clock driver has output frequencies of up to 133 MHz and output to output skews of less than 250 ps. The CY2509/10 provides minimum cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications.

• Spread Aware™ designed to work with spread spectrum frequency timing generator (SSFTG) reference signals
• Well suited to both 100- and 133-MHz designs Ten (CY2509) or eleven (CY2510) low-voltage complementary metal oxide semiconductor (LVCMOS) / low-voltage transistortransistor logic (LVTTL) outputs.
• 50 ps typical peak cycle-to-cycle jitter
• Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs
• 3.3 V power supply
• On-chip 25 O damping resistors
• Available in 24-pin thin shrunk small outline package (TSSOP) package
• Improved tracking skew, but narrower frequency support limit when compared to W132-09B/10B