Zero Delay PLL Clock Buffer Single 32-Pin TQFP

The CY7B9950 RoboClock is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the clock tree design of high performance computer and communication systems. The user can program the phase of the output banks through nF[0:1] pins. The adjustable phase feature enables the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to the feedback input to achieve different reference frequency multiplications, divide ratios, and zero input-output delay. The device also features split output bank power supplies, which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising or falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from ± 12 mA to ± 24 mA(3.3 V).

• 2.5 V or 3.3 V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• 50 ps typical matched-pair output-output skew
• 50 ps typical cycle-cycle jitter
• 49.5 / 50.5% typical output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50??terminated lines
• LVCMOS / LVTTL overvoltage tolerant reference input
• Phase adjustments in 625 / 1250 ps steps up to +7.5 ns
• 2×, 4× multiply and (1/2)×, (1/4)× divide ratios
• Spread spectrum compatible
• Industrial temperature range: -40 °C to +85 °C
• 32-pin TQFP package