Zero Delay PLL Clock Buffer Single 32-Pin TQFP

The CY29653 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29653 features an LVPECL reference clock input and provides eight outputs plus one feedback output. VCO output divides by four or eight per VCO_SEL setting (see the Function Table). Each LVCMOS-compatible output can drive 50? series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:16. The PLL is ensured stable given that the VCO is configured to run between 140 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 125 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. When BYPASS# is set LOW, PLL and output dividers are bypassed resulting in a 1:9 LVPECL to LVCMOS high performance fanout buffer. For normal PLL operation both PLL_EN and BYPASS# are set HIGH

• Output frequency range: 25 MHz to 125 MHz
• Input frequency range (÷4): 35 MHz to 125 MHz
• Input frequency range (÷8): 25 MHz to 62.5 MHz
• 3.3V operation
• Eight Clock outputs: Drive up to 16 clock lines
• One feedback output
• LVPECL reference clock input
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9653 and MPC953
• Industrial temperature range: -40°C to +85°C
• 32-pin 1.0-mm TQFP package