Zero Delay PLL Clock Buffer Single 28-Pin SSOP

The CY23FS08 is a FailSafe Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock.

• Zero input-output propagation delay
• 100 ps typical output cycle-to-cycle jitter
• 110 ps typical output-output skew
• 1 MHz to 200 MHz reference input
• Supports industry standard input crystals
• 200 MHz (commercial), 166 MHz (industrial) outputs
• 5 V tolerant inputs
• Phase-locked loop (PLL) bypass mode
• Dual reference inputs
• 28-pin SSOP
• Split 2.5 V or 3.3 V output power supplies
• 3.3 V core power supply
• Industrial temperature available