Zero Delay PLL Clock Buffer Single 16-Pin TSSOP T/R

The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps.

• 1:8 outputs LVCMOS zero-delay buffer
• Zero input-output propagation delay, adjustable by the capacitive load on FBK input
• Multiple Configurations, see Table 2
• Multiple low-skew outputs
• 200 ps max output-output skew
• 700 ps max device-device skew
• Two banks of four outputs, output tristate control by two select inputs
• Supports a clock I/O frequency range of 10 MHz to 133 MHz
• Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H)
• ±250 ps static phase offset (SPO)
• 16-pin SOIC package or 16-pin TSSOP package
• Single 3.3 V supply
• Ambient temperature range: -40°C to +85°C
• Compatible with the CY2308 and CY23S08
• Spread spectrum compatible