Zero Delay PLL Clock Buffer Single 10MHz to 140MHz 16-Pin SOIC

The CY23S08 is a 3.3-V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and obtained from one of the outputs. The input-to-output propagation delay is less than 350 ps and output-to-output skew is less than 250 ps. The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Select Input Decoding on page 4. If all output clocks are not required, Bank B can be tristated. The select inputs also enable the input clock to be directly applied to the output for chip and system testing purposes. The CY23S08 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are tristated and the PLL is turned off, resulting in less than 50 mA of current draw. Multiple CY23S08 devices accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is less than 700 ps. The CY23S08 is available in five different configurations.

• Zero input output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations
• Multiple low-skew outputs
  • 45-ps typical output-output skew (-1)
  • Two banks of four outputs that can be tristated by two select inputs
• 10 MHz to 140 MHz operating range
• Advanced 0.65-µm complementary metal oxide semiconductor (CMOS) technology
• Space-saving 16-pin small outline integrated circuit (SOIC) package
• 3.3-V operation
• Spread Aware