Video Decoder 100-Pin LQFP

The SAA7114 is a video capture device for applications at the image port of Video Graphics Array (VGA) controllers. The SAA7114 is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit. It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU 601 compatible color component values. The SAA7114 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals. An expansion port (X port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or a video phone codec. At the so called image port (I port) the SAA7114 supports 8-bit or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for the SAA7114 is to capture and scale video images, to be provided as a digital video stream through the image port of a VGA controller, for display via the frame buffer of the VGA, or for capture to system memory. In parallel the SAA7114 also incorporates provisions for capturing the serially coded data in the Vertical Blanking Interval (VBI) data. Two principal functions are available: To capture raw video samples, after interpolation to the required output data rate, via the scaler A versatile data slicer (data recovery) unit

• Six analog inputs, internal analog source selectors, 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS)
• Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters
• Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel
• Automatic Clamp Control (ACC) for CVBS, Y and C
• Switchable white peak control
• Two 9-bit video CMOS ADCs, digitized CVBS or Y/C signals are available on the expansion port
• On-chip line-locked clock generation in accordance with “ITU 601”
• Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
• Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards
• Horizontal and vertical sync detection
• Automatic detection of 50 Hz and 60 Hz field frequency, and automatic switching between PAL and NTSC standards
• Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation
  • Increased luminance and chrominance bandwidth for all PAL and NTSC standards
  • Reduced cross color and cross luminance artefacts
• PAL delay line for correcting PAL phase errors
• Independent Brightness Contrast Saturation (BCS) adjustment for decoder part
• User programmable sharpness control
• Independent gain and offset adjustment for raw data path
• 2.5 Digital I/O interfaces
• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.
• Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-CB-CR:
• Output from decoder part, real-time and unscaled
• Input to scaler part
• Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals