USB Streaming Controller 48-Pin TQFP

The TAS1020 integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed specifically for applications that require isochronous data streaming. Applications include digital speakers, which require the streaming of digital audio data between the host PC and the speaker system via the USB connection. The TAS1020 device is fully compatible with the USB Specification Version 1.1 and the USB Audio Class Specification. The TAS1020 uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization, the boot loader program downloads the application program code to a 6K RAM from either the host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk end-point transactions. In addition, the MCU can handle USB isochronous end-point transactions. The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition to the USB control end-point, support is provided for up to seven in end-points and seven out end-points. The USB end-points are fully configurable by the MCU application code using a set of end-point configuration blocks that reside in on-chip RAM. All USB data transfer types are supported. The TAS1020 device also includes a codec port interface (C-Port) that can be configured to support several industry standard serial interface protocols. These protocols include the audio codec (AC) "97 Revision 1.X, the audio codec (AC) "97 Revision 2.X and several inter-IC sound (I2S) modes. A direct memory access (DMA) controller with two channels is provided for streaming the USB isochronous data packets to/from the codec port interface. Each DMA channel can support one USB isochronous end-point. An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization modes, which include asynchronous, synchronous and adaptive. Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit general-purpose input/output (GPIO) ports. The TAS1020 device is implemented in a 3.3-V 0.25 um CMOS technology.

Universal Serial Bus (USB)

• USB specification version 1.1 compatible
• USB audio class specification 1.0 compatible
• Integrated USB transceiver
• Supports 12 Mb/s data rate (full speed)
• Supports suspend/resume and remote wake-up
• Supports control, interrupt, bulk, and isochronous data transfer types
• Supports up to a total of seven in end-points and seven out end-points in addition to the control end-point
• Data transfer type, data buffer size, single or double buffering is programmable for each end-point
• On-chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive synchronization modes for isochronous end-points
• To support synchronization for streaming USB audio data, the ACG can be used to generate the master clock for the codec

Micro-Controller Unit (MCU)

• Standard 8052 8-bit core
• 8K bytes of program memory ROM that contains a boot loader program and a library of commonly used USB functions
• 6016 bytes of program memory RAM which is loaded by the boot loader program
• 256 bytes of internal data memory RAM
• Two GPIO ports
• MCU handles all USB control, interrupt, and bulk end-point transfers

DMA Controller

• Two DMA channels to support streaming USB audio data to/from the codec port interface
• Each channel can support a single USB isochronous end-point
• In the I²S mode the device can support DAC/ADCs at different sampling frequencies
• A circular programmable FIFO used for isochronous audio data streaming

Codec Port Interface

• Configurable to support AC"97 1.X, AC"97 2.X, AIC or I²S serial interface formats
• I²S modes can support a combination of one DAC and/or two ADCs
• Can be configured as a general-purpose serial interface
• Can support bulk data transfer using DMA for higher throughput

I²C Interface

• Master only interface
• Does not support a multimaster bus environment
• Programmable to 100 kb/s or 400 kb/s data transfer speeds
• Supports I² C arbitration and wait states to accomodate slow slaves

General Characteristics

• High performance 48-pin TQFP Package
• On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz crystal input
• Reset output available which is asserted for both system and USB reset
• External MCU mode supports application firmware development
• 8K ROM with boot loader program and commonly used USB functions library
• 3.3 V core and I/O buffers