Universal Serial Bus Host Controller 128-Pin LQFP T/R

The SAF1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic processor interface. It integrates one Enhanced Host Controller Interface (EHCI), one Transaction Translator (TT) and three transceivers. The host controller portion of the SAF1760 and the three transceivers comply to Universal Serial Bus Specification Rev. 2.0. The EHCI portion of the SAF1760 is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The integrated high-performance Hi-Speed USB transceivers enable the SAF1760 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The three downstream ports allow simultaneous connection of three devices at different speeds (high-speed, full-speed and low-speed). The generic processor interface allows the SAF1760 to be connected to various processors as a memory-mapped resource. The SAF1760 is a slave host: it does not require bus-mastering capabilities of the host system bus. The interface can be configured, ensuring compatibility with a variety of processors. Data transfer can be performed on 16 bits or 32 bits, using Programmed Input/Output (PIO) or Direct Memory Access (DMA) with major control signals configurable as active LOW or active HIGH. Integration of the TT allows connection to full-speed and low-speed devices, without the need of integrating Open Host Controller Interface (OHCI) or Universal Host Controller Interface (UHCI). Instead of dealing with two sets of software drivers, EHCI and OHCI or UHCI, you need to deal with only one set, EHCI, that dramatically reduces software complexity and IC cost.

• Automotive qualified in accordance with AEC-Q100
• The host controller portion of the SAF1760 complies with Universal Serial Bus Specification Rev. 2.0
• The EHCI portion of the SAF1760 is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0
• Contains three integrated Hi-Speed USB transceivers that support high-speed, full-speed and low-speed modes
• Integrates a TT for original USB (full-speed and low-speed) device support
• Up to 64 kB internal memory (8 k x 64 bit) accessible through a generic processor interface; operation in multitasking environments is made possible by the implementation of virtual segmentation mechanism with bank switching on task request
• Generic processor interface, non-multiplexed and variable latency, with a configurable 32-bit or 16-bit external data bus; the processor interface can be defined as variable-latency or SRAM type (memory mapping)
• Slave DMA support to reduce the load of the host system CPU during the data transfer to or from the memory
• Integrated Phase-Locked Loop (PLL) with a 12 MHz crystal or an external clock input
• Integrated multi-configuration FIFO
• Optimized msec-based or multi-msec-based Proprietary Transfer Descriptor (PTD) interrupt
• Tolerant I/O for low voltage CPU interface (1.65 V to 3.6 V)
• 3.3 V-to-5.0 V external power supply input
• Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for low-power core)
• Internal power-on reset and low-voltage reset
• Supports suspend and remote wake-up
• Target current consumption:
  • Normal operation; one port in high-speed active: I_CC< 100 mA
  • Suspend mode: I_CC(susp)< 150 µA at room temperature
• Built-in configurable overcurrent circuitry (digital or analog overcurrent protection)