UART 1-CH 16Byte FIFO 5V 40-Pin PDIP Rail

The PC16550D device is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART). Functionally identical to the 16450 on powerup (CHARACTER mode: can also be reset to 16450 Mode under software control) the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead.In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216–1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The UART has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be programmed to the user’s requirements, minimizing the computing required to handle the communications link. The UART is fabricated using Texas Instruments advanced M2CMOS process.

Capable of Running All Existing 16450 Software.

Pin for Pin Compatible With the Existing 16450
Except for CSOUT (24) and NC (29). The Former
CSOUT and NC Pins Are TXRDY and RXRDY,
Respectively.

After Reset, All Registers Are Identical to the
16450 Register Set.

In the FIFO⁽¹⁾ Mode Transmitter and Receiver Are
Each Buffered With 16 Byte FIFO’s to Reduce the
Number of Interrupts Presented to the CPU.

Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and Parity) to or
From the Serial Data.

Holding and Shift Registers in the 16450 Mode
Eliminate the Need for Precise Synchronization
Between the CPU and Serial Data.

Independently Controlled Transmit, Receive, Line
Status, and Data Set Interrupts.

Programmable Baud Generator Divides Any Input
Clock by 1 to (2¹⁶ – 1) and Generates the 16 ×
Clock.

Independent Receiver Clock Input.

MODEM Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD).

Fully Programmable Serial-Interface
Characteristics

• 5-, 6-, 7-, or 8-Bit Characters
• Even, Odd, or No-Parity Bit Generation and
  Detection
• 1-, 1 1/2-, or 2-Stop Bit Generation
• Baud Generation (DC to 1.5 M Baud).

False Start Bit Detection.

Complete Status Reporting Capabilities.

TRI-STATE TTL Drive for the Data and Control
Buses.

Line Break Generation and Detection.

Internal Diagnostic Capabilities

• Loopback Controls for Communications Link
  Fault Isolation
• Break, Parity, Overrun, Framing Error Simulation.

Full Prioritized Interrupt System Controls.