SRAMs (asynchronous)

The IS62WV25616DBLL are high-speed, low power, 256M bit SRAMs organized as words by 16 bits. It is fabricated using high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselcted) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable(WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62WV25616DBLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm) .

• High-speed access time: 35, 45, 55 ns
• CMOS low power operation
  • 30 mW (typical) operating
  • 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply 2.3V-3.6V Vdd
• Fully static operation: no Clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Commercial and Industrial temperature support
• Lead-free available
• 2 CS option available