SRAMs (asynchronous)

The IS62C5128BL are high-speed, 4,194,304-bit static RAMs organized as 524,288 words by 8 bits. They are fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 45ns with low power consumption. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE\ and OE\. The active LOW Write Enable (WE\) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62C5128BL are packaged in the JEDEC standard 32-pins TSOP-I, 32-pin SOP and 32-pin TSOP-II packages.

• High-speed access time: 45ns
• Low Active Power: 50 mW (typical)
• Low Standby Power: 10 mW (typical) CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refreshrequired
• Available in 32-pin sTSOP-I, 32-pin SOP and32-pin TSOP-II packages
• Commercial, Industrial and Automotive temperatureranges available
• Lead-free available