SLIC/CODEC DPLL

The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable.

• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
• Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse
• Automatic entry and exit from freerun mode on reference fail
• Provides DPLL lock and reference fail indication
• DPLL bandwidth of 29 Hz for all rates of input references
• Less than 0.6 nsecpp intrinsic jitter on all output clocks
• 20 MHz external master clock source: clock oscillator or crystal
• Simple hardware control interface