Shift Register Single 8-Bit Serial/Parallel to Serial 16-Pin TVSOP T/R

The "LV165 parallel-load, 8-bit shift registers are designed for 2.7-V to 5.5-V VCC operation.When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD\ input. The "LV165 feature a clock inhibit function and a complemented serial output Q\H.Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is held low independently of the levels of CLK, CLK INH, or SER.The SN54LV165 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV165 is characterized for operation from -40°C to 85°C.

EPIC^TM (Enhanced-Performance Implanted CMOS) 2-uProcess

Typical V_OLP (Output Ground Bounce)< 0.8 V atV_CC, T_A = 25°C

Typical V_OHV (Output V_OH Undershoot)<2 V at V_CC, T_A = 25°C

ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015;Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17

Package Options Include Plastic Small-Outline (D), ShrinkSmall-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat(W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs