Shift Register Single 8-Bit Serial to Parallel 14-Pin SOP T/R

This 8-bit parallel-out serial shift register featuresAND-gated serial (A and B) inputs and anasynchronous clear (CLR) input. The gated serialinputs permit control over incoming data because a low at either input inhibits entry of the new data and resetsthe first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, whichdetermines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transitionof the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.

• AND-Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Direct Clear
• Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs