Serial Communication Adapter 84-Pin PLCC

The HD64570 has a four on-chip direct memory access controller channels (DMAC channels 0–3), which support chained-block transfer. Channel 0 is connected to the MSCI channel 0 receiver, channel 1 to the MSCI channel 0 transmitter, channel 2 to the MSCI channel 1 receiver, and channel 3 to the MSCI channel 1 transmitter. Other than the connection destination, the specifications for the four channels are identical.

• Data transfer rate:
  • 50 bits/s to 7.1 Mbits/s (f = 10 MHz),
  • 50 bits/s to 12 Mbits/s (f = 16.7 MHz),
  • 50 bits/s to 5.7 Mbits/s (f = 8 MHz)
• Protocol support
  • Asynchronous (ASYNC): 5 to 8 bits + parity
  • Byte synchronous (COP): bisync, X.21, DDCMP, etc.
  • Bit synchronous (BOP): frame relay, HDLC, ?SDLC, X.25 link level (LAPB), LAPD etc.
• Highly efficient data transfer: two 32-byte FIFOs (transmit/receive) per channel
• Error detection: parity (asynchronous)