Reprogrammable Connectivity Processor 48-Pin LAM CSP T/R

The CP3CN17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high computing bandwidth, hardware communications peripherals for high I/O bandwidth, and an external bus for system expandability. On-chip communications peripherals include: CAN controller, ACCESS.bus, Microwire/Plus, SPI, UART, and Advanced Audio Interface (AAI). Additional on-chip peripherals include DMA controller, CVSD/PCM conversion module, Timing and Watchdog Unit, Versatile Timer Unit, Multi- Function Timer, and Multi- Input Wakeup. The CP3CN17 is backed up by the software resources designers need for rapid time-to-market, including an operating system, peripheral drivers, reference designs, and an integrated development environment. Texas Instruments Incorporated offers a complete and industry-proven application development environment for CP3CN17 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Development Board, and Application Software.

CPU Features

• Fully static RISC processor core, capable of operating
  from 0 to 24 MHz with zero wait/hold states
• Minimum 41.7 ns instruction cycle time with a 24 MHz internal
  clock frequency, based on a 12 MHz external input
• 30 independently vectored peripheral interrupts

On-Chip Memory

• 256K bytes reprogrammable Flash program memory
• 8K bytes Flash data memory
• 10K bytes of static RAM data memory
• Addresses up to 8 MB of external memory

Broad Range of Hardware Communications Peripherals

• Full CAN interface with 15 message buffers conforming to
  CAN specification 2.0B active
• ACCESS.bus serial bus (compatible with Philips I2C bus)
• 8/16-bit SPI, Microwire/Plus serial interface
• Universal Asynchronous Receiver/Transmitter (UART)
• Advanced Audio Interface (AAI) to connect to external
  8/ 13-bit PCM Codecs as well as to ISDN-Controllers
  through the IOM-2 interface (slave only)
• CVSD/PCM converter supporting one bidirectional audio connection

General-Purpose Hardware Peripherals

• Dual 16-bit Multi-Function Timer
• Versatile Timer Unit with four subsystems (VTU)
• Four channel DMA controller
• Timing and Watchdog Unit

Flexible I/O

• Up to 40 general-purpose I/O pins (shared with on-chip peripheral I/O pins)
• Programmable I/O pin characteristics: TRI-STATE output, push-pull output, weak
  pull-up input, high-impedance input
• Schmitt triggers on general purpose inputs
• Multi-Input Wakeup

Extensive Power and Clock Management Support

• On-chip Phase Locked Loop
• Support for multiple clock options
• Dual clock and reset
• Power-down modes

Power Supply

• I/O port operation at 2.5 V to 3.3 V
• Core logic operation at 2.5 V
• On-chip power-on reset

Temperature Range

• –40°C to +85°C (Industrial)

Packages

• CSP-48, LQFP-100

Complete Development Environment

• Pre-integrated hardware and software support for rapid prototyping and
  production
• Integrated environment
• Project Manager
• Multi-file C source editor