RENR5F10EBEANA#W0
RENR5F10EBEANA#W0
- Minimum instruction execution time can be changed from high speed (0.03125 µs: @ 32 MHz operation with high speed on-chip oscillator clock or PLL clock) to ultra low-speed (66.6 µs: @ 15 kHz operation with low-speed on-chip oscillator clock)
- General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
- ROM: 16 to 256 KB
- RAM: 1 to 20 KB
- Data flash memory: 4 KB/8 KB
- High-speed on-chip oscillator clock
- Selectable from 32 MHz (Typ.), 24 MHz (Typ.), 16 MHz (Typ.), 12 MHz (Typ.), 8 MHz (Typ.), 4 MHz (Typ.), and 1 MHz (Typ.) (Selectable from 64 MHz (Typ.) and 48 MHz (Typ.) when using Timer RD)
- Low-speed on-chip oscillator clock: 15 kHz × 2 channels (one for WWDT and one for CPU and peripherals other than WWDT)
- On-chip PLL (×3, ×4, ×6, ×8)
- On-chip single-power-supply flash memory (with prohibition of block erase/writing function)
- Self-programming (with boot swap function/flash shield window function)
- On-chip debug function
- On-chip power-on-reset (POR) circuit and voltage detector (LVD)
- On-chip watchdog timer (operable with the dedicated low-speed on-chip oscillator clock)
- Multiply/divide/multiply & accumulate instructions are supported
- 16 bits × 16 bits = 32 bits (Unsigned or signed)
- 32 bits ÷ 32 bits = 32 bits (Unsigned)
- 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
- On-chip key interrupt function
- On-chip clock output/buzzer output controller
- On-chip BCD adjustment
- I/O ports: 16 to 92 (including one input-only pin)
- Timer
- 16-bit timer array unit: 8 to 16 channels
- 16-bit timer RD: 2 channels (six triangle-wave outputs; saw tooth wave/triangle-wave modulation)
- 16-bit timer RJ: 1 channel
- Watchdog timer: 1 channel
- Real-time clock: 1 channel
- Serial interface
- CSI
- UART/UART (LIN-bus supported)
- LIN module (master/slave supported)
- I2C/simplified I2C
- CAN interface (RS-CAN lite)
- 8/10-bit resolution A/D converter (VDD = 2.7 to 5.5 V): 4 to 31 channels
- DTC (Max. 52 sources)
- ELC (Max. 26 channels for event link source, Max. 9 channels for event link destination)
- Safety functions (CRC calculation, PLL lock detection, AD test, SFR guard, etc.) RL78/F13, F14
- 8-bit D/A converter
- On-chip comparator: 1 channel (input pin: 4 channels)
- Power supply voltage: VDD = 2.7 to 5.5 V
- Operating ambient temperature: TA = -40 to +105ºC (grade L)/TA = -40 to +125°C (grade K)/TA = -40 to +150ºC (grade Y)
Характеристики
| Бренд | Renesas Electronics |
|---|---|
| Schedule B | 8542310000 |
| HTSN | 8542310001 |
| Program M | 8 KB |
| Minimum O | 1.6 V |
| Screening Level | Industrial |
| Device Core | RL78 |
| On Chip Adc | 18-chx12-bit |
| Maximum O | 3.6 V |
| Рабочая температура | -40 to 85 °C |
| Watchdog | 1 |
| Operating | 1.8, 2.5, 3.3 V |
| Program M | Flash |
| Ram Size | 0.5 KB |
| Number Of | 26 |
| Data Bus Width | 16 Bit |
| Maximum E | 1 MB |
| Instructi | CISC |
| Interface Type | CSI/I2C/LIN/UART |
| Number Of | 13 |
| Maximum Speed | 32 MHz |
| Family | R5F10E |
| Упаковка | Embossed Tape and Reel |
| Data Memo | 4 KB |
| Display Driver | 1 |
| Lcd Segments | 156|280 |
SKU: R5F10EBEANA#W0