Registered Buffer Single 25-CH CMOS 96-Pin BGA MICROSTAR T/R

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared and the data outputs are driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTU32864C must ensure that the outputs remain low, thus ensuring no glitches on the output.

• Member of the Widebus+™ Family
• Pinout Optimizes DDR2 DIMM PCB Layout
• Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
• Chip-Select Inputs Gate Data Outputs From Changing State and Minimize System Power Consumption
• Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated Line
• Supports SSTL_18 Data Inputs
• Differential Clock (CLK and CLK) Inputs
• Supports LVCMOS Switching Levels on Control and RESET Inputs
• RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 5000-V Human-Body Model (A114-A)
  • 150-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)