Real Time Clock Parallel 48-Pin TQFP

S1 s n, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD fo at. Corrections for day of month and leap year are made automatically. The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0–A18. W n any the ES IPTI The D 558 i a full-functio rm he of upper 16 address locations are accessed, the DS1558 inhibits CER and OER to the S M, an dir DS1558 can be used w SRA up addresses. Smaller SRAMs can be used, provided that the unused upper address lines on the DS1558 are connected to VCC. The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow th ser to ess static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC in ation is always maintained. The DS1558 has interrupt ( RA d re ects reads and writes to the RTC registers within the DS1558. The ith Ms to 524,272 e u acc form IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity. The IRQ / ter terrupt when the RTC register values m h use grammed alarm values. The interrupt is always available while the device is powered from th ystem ply, and it can be programmed to occur when in the battery-backed state to serve as a wake-up. The FT in rupt output can be used to generate an external in atc r-pro e s sup system IRQ /FT output can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt or reset output are activated if the correct activity is not detected within programm i ower-down or failure and hold the CPU ; the ed lim ts. The DS1558 power-on reset can be used to detect a system p in a safe reset state until normal power returns and stabilizes RST output is used for this function. T DS155 also tects the data in the clock and SRAM against out-of-tolerance V conditions by inhibiting the he 8 contains its own power-fail circuitry, which automatically pro CCI CE input when the VCC supply enters an out-of-tolerance condition. W T, the external battery is s hed u ovides a high degree of data security during unpredictable CC levels. hen VCCI goes below the level of VBA witc on to s pply energy to the clock and the external SRAM. This feature pr system operation brought on by low V

• Integrated Real-Time Clock (RTC), PowerFail Control Circuit, and NV RAM Controller
• Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the 16 Top RAM Locations
• Century Register
• Greater than 10 Years of Timekeeping and Data Retention in the Absence of Power with Small Lithium Coin Cell(s) and Low-Leakage SRAM
• Precision Power-On Reset
• Programmable W Alarm
• BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic LeapYear Compensation Valid Up t0 the Year 2100
• Battery Voltage-Level Indicator Flag
• Power-Fail Write Protection Allows for ?10% VCC Power-Supply Tolerance
• Underwriters Laboratory (UL) Recognized