PSRAM Sync 384M-Bit 56-Pin VFBGA

Micron"s 65nm device is the latest generation of StrataFlash memory featuring flexible, multiple-partition, dual-operation architecture. The device provides high-performance, asynchronous read mode and synchronous-burst read mode using 1.8V low-voltage, multilevel cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while PROGRAM and ERASE operations take place in the background. The multiple partitions allow flexibility for system designers to choose the size of the code and data segments. The device is manufactured using 65nm process technologies and is available in industry- standard chip scale packaging.

• Micron® Parallel NOR Flash and PSRAM Components
• RoHS-compliant, “green” package
• Multiplexed address/data bus
• Deep power-down (DPD) mode on both devices
• oNOR: 2µA (TYP)
• oPSRAM: 10µA (TYP)
• Space-saving multichip package (MCP)
• Low-voltage operation (1.70–1.95V)
• Industrial temperature range: –40°C to +85°C
• NOR Flash-Specific Features
• 256Mb or 512Mb multiple-bank, Parallel NOR Flash
• Synchronous/asynchronous read
  • Synchronous burst reads: 133 MHz (266MB/sec)
  • Random access times: 96ns
• Programming times
  • 2.0 µs/word (TYP) buffered programming
  • 0.9 s/block (TYP) for block erase
  • 20µs (TYP) program/erase suspend
  • 10µs by word (TYP) for fast factory program
  • Double/quadruple word program option
• Memory blocks
  • Multiple bank memory array: Eight 32Mb banks
  • Uniform blocks1
• Synchronous burst read suspend
• Dual operations
  • Program erase in 1 bank, read in others
  • No delay between READ and WRITE operations
• Block locking
  • All blocks locked at power-up
  • Any combination of blocks can be locked
  • WP# for block lock-down
• Security
  • 2112-bit user programmable OTP cells
  • 64-bit unique device number
• Common Flash interface
• 100,000 PROGRAM/ERASE cycles per block
• Electronic signature
  • 256Mb: 8904h
  • 512Mb: 9815h
• PSRAM-Specific Features
• Synchronous/asynchronous read
  • Synchronous burst read mode: 133 MHz
  • Random access: 70ns
  • Asynchronous page mode: 20ns
• Partial-array self refresh (PAR)
• Automatic temperature-compensated self-refresh (TCR)