Processor Power Management Subsystem 81-Pin QFN EP

The WM8326 is an integrated power-management subsystem which provides a cost-effective, flexible, single-chip solution for power management. It is specifically targeted at the requirements of a range of low-power portable consumer products, but is suitable to any application with a multimedia processor. The WM8326 is designed to operate as a system PMIC supporting the ARM9, ARM11 and ARM Cortex-A processors, but is also capable of supporting the majority of application and mobile processors at the heart of a wide range of low-power consumer multimedia applications. The start-up behaviour and configuration is fully programmable in an integrated OTP non-volatile memory. This highly flexible solution helps reduce time-to-market, as changing application requirements can be very easily accommodated in the OTP. The InstantConfigTM interface enables an external EEPROM to configure the WM8326. The WM8326 power management subsystem comprises four programmable DC-DC converters and eleven LDO regulators (four of which are low-noise for supplying sensitive analogue subsystems). The integrated OTP bootstrap circuitry controls the start-up sequencing and voltages of the converters and regulators as well as the sequencing of system clocks. The DC-DC converters deliver high performance and high efficiency across a wide range of operating conditions. They are optimised to support the high load current transients seen in modern processor core domains. DC-DC3 / DC-DC4 can be connected together and operated in ‘dual’ mode to support an increased current load of up to 1.6A. An on-chip regulator provides power for always-on PMIC functions such as register map and the RTC. The device provides autonomous backup battery switchover. A low-power LDO is included to support ‘Alive’ processor power domains external to the WM8326. A 12-bit Auxiliary ADC supports a wide range of applications for internal as well as external analogue sampling, such as voltage detection and temperature measurement.

• Power Management
  • 2 x DC-DC synchronous buck converters (0.6V - 1.8V, 2.5A, DVS)
  • 2 x DC-DC synchronous buck converters (0.85V - 3.4V, 1A)
  • 1 x LDO regulator (0.9V - 3.3V, 300mA, 1?)
  • 2 x LDO regulators (0.9V - 3.3V, 200mA, 1?)
  • 3 x LDO regulators (0.9V - 3.3V, 100mA, 2?)
  • 2 x Low-noise LDO regulators (1.0V - 3.5V, 200mA, 1?)
  • 2 x Low-noise LDO regulators (1.0V - 3.5V, 150mA, 2?)
  • 1 x ‘Alive’ regulator (0.8V – 1.55V, up to 25mA)
• System Control
  • I2 or SPI compatible primary control interface
  • Comprehensive interrupt scheme
  • Watchdog timer and system reset control
  • Autonomous power sequencing and fault detection
  • OTP memory bootstrap configuration function
• Additional Features
  • Auxiliary ADC for multi-function analogue measurement
  • 128-bit pseudo-random unique ID
  • Secure Real-Time Clock with wake-up alarm
  • 12 x configurable multi-function (GPIO) pins
  • Comprehensive clocking scheme: low-power 32kHz RTC crystal oscillator, GPIO clock output and 4MHz RC clock for power management
  • System LED outputs indicating device power state, and fault status
• Package Options
  • 8 x 8 x 0.85mm, 81-lead QFN package