PLL Clock Driver Single 56-Pin TSSOP T/R

PI6C21200 is a high-speed, low-noise PCIe differential clock buffer designed to be a companion with PI6C410B clock synthesizer. The device distributes twelve copies of the differential SRC clock coming from PI6C410B. The output frequency can be ratioed to offer a derivative frequency from the input frequency. Each differential output is controlled by individual OE pin, except OUT10 and OUT11 are sharing one OE_10#_11# pin. The clock outputs are controlled by input selection of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.

• Twelve Pairs of PCIe Differential Clocks (HCSL compatible signaling)
• Low skew < 50ps
• Low jitter < 50ps
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fan out operation
• Gear Ratio supporting different output frequencies
• 3.3V Operation
• 56-pin Package (Pb-Free & Green): TSSOP (A56)