PLL Clock Driver Single 100MHz 28-Pin SSOP

PI6C20400A is a PCIe 2.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PI6C410BS. The device distributes the differential SRC clock from PI6C410BS to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tristated. When PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.

• Phase jitter filter for PCIe® 2.0 application
• Four Pairs of Differential Clocks
• Low skew < 50ps
• Low jitter < 50ps cycle-to-cycle
• < 1 ps additive RMS phase jitter
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Programmable PLL Bandwidth
• 100 MHz PLL Mode operation
• 100 - 400 MHz Bypass Mode operation
• 3.3V Operation
• Packaging (Pb-free and Green): ?28-Pin SSOP (H28) ?28-Pin TSSOP (L28)