PHY 4-CH 289-Pin BGA

The TLK3104SCGNT is a flexible four-channel serial backplane transceiver, delivering high-speed bidirectionalpoint-to-point data and transmissions providing up to 10 Gbps of data transmission capacity. TheTLK3104SCGNT supports an operating range of serial data rates from 3.1 Gbps to 3.125 Gbps. The primaryapplication of this device is to provide building blocks for developing point-to-point baseband data transmissionover controlled impedance media of approximately 50 ?. The transmission media can be printed-circuit boardtraces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent uponthe attenuation characteristics of the media and the noise coupling to the environment.The TLK3104SCGNT performs the parallel-to-serial, serial-to-parallel conversion, and clock extractionfunctions for a physical layer interface. The TLK3104SCGNT also provides an 8-bit/10-bit (8-b/10-b)encode/decode function. The serial transmitter and receiver use differential PECL compatible signalings. Theparallel interface supports a low voltage differential signaling (LVDS) interface. The purpose of the interface isto provide a simple, inexpensive, and easy-to-implement interconnection between the controller and PHY. TheLVDS interface supports independent 4-bit wide transmit and receive data paths for full-duplex operation.The TLK3104SCGNT provides a comprehensive series of built-in tests for self-test purposes including internalserial loopback and PRBS generation and verification. An IEEE 1149.1 JTAG port is also supported.TLK3104SCGNT also has an MDIO/MDC serial port to provide certain control functions.The TLK3104SCGNT operates with a single 2.5-V supply and dissipates less than 3 W. The device is packagedin a 19 × 19 mm, 289 pin plastic ball grid array (PBGA) package and is characterised for operation from -40°Cto 75°C.

• 3.125 Gbps Per Port Providing 10-Gbps Data Throughput
• Support Transmit Only, Receiver Only, Transceiver and Repeater Functions in a Single Chip Through Configuration Pins
• Selectable Independent Channel or Channel Sync Operation
• On-Chip Termination for LVDS and PECL Compatible Interface
• On-Chip 8-Bit/10-Bit Coding
• Hot Plug Protection
• Interfaces to Backplane, Copper Cables, or Optical Modules
• Receiver Differential Input Thresholds 150 mV Min
• PECL Compatible Differential Signaling for Serial Interface With Programmable Preemphasis
• ESD Protection 2 kV
• Low Power 4-Bit LVDS Parallel Interface
• Typical Power Consumption < 675 mW/Port at 3.125 Gbps Under Transceiver Mode
• CMOS Technology
• Able to Operate With a Single 2.5-V Power Supply
• Low Cost 289 Ball PBGA Package
• No External Filter Capacitors Required
• On-Chip PRBS Generation and Verification
• JTAG Test Support
• Flow Through Pinout