PHY 3-CH 400-Pin TE-BGA

The DS3163 integrate ATM cell/HDLC packet processor(s) with DS3/E3 framer(s) to map/demap ATM cells or packets into as many as four DS3/E3 digital lines with DS3-framed, E3-framed, or clear- channel data streams on per-port basis.

• Triple ATM/Packet PHYs for DS3, E3, and Clear-Channel 52Mbps (CC52)
• Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform
• Each Port Independently Configurable
• Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams
• UTOPIA L2/L3 or POS-PHY L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width
• 66MHz UTOPIA L3 and POS-PHY L3 Clock
• 52MHz UTOPIA L2 and POS-PHY L2 Clock
• Ports Independently Configurable for Cell or Packet Traffic in POS-PHY Bus Modes
• Direct, PLCP, DSS, and Clear-Channel Cell Mapping
• Direct and Clear-Channel Packet Mapping
• On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or G.832) Framer(s)
• Ports Independently Configurable for DS3, E3 (Full or Subrate) or Arbitrary Framing Protocols Up to 52Mbps
• Programmable (Externally Controlled or Internally Finite State Machine Controlled) Subrate DS3/E3