PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY

The Am79C975 controllers is singlechip 32-bit full- duplex, 10/100-Megabit per second (Mbps) fully integrated PCI-to-Wire Fast Ethernet system solution, designed to address high-performance system application requirements. They are flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput and low CPU and system bus utilization. The Am79C973 and Am79C975 controllers are fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications. The third generation Am79C973 and Am79C975 Fast Ethernet controllers also have several enhancements over their predecessors, the Am79C971 and Am79C972 devices. Besides integrating the complete 10/100 Physical Layer (PHY) interface, they further reduce system implementation cost by integrating the SRAM buffers on chip. The Am79C975 controller contain 12- kilobyte (Kbyte) buffers, the largest of their class in 10/ 100 Mbps Ethernet controllers. The large internal buffers are fully programmable between the RX and TX queues for optimal performance. The Am79C975 controller is also compliant with PC98/PC99 and Wired for Management specifications. They fully support Microsoft’s OnNow and ACPI specifications, which are backward compatible with Magic Packet technology and compliant with the PCI Bus Power Management Interface Specification by supporting the four power management states (D0, D1, D2, and D3), the optional PME pin, and the necessary configuration and data registers. The Am79C975 controller is complete Ethernet nodes integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)- compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY. The integrated 10/100 PHY unit of the Am79C973 and Am79C975 controllers implement the complete physical layer for 10BASE-T and the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) functionality for 100BASE-TX, including MLT-3 encoding/decoding. It also supports 100BASE-FX operation by providing a Pseudo-ECL (PECL) interface for direct connection to a fiber optic transceiver module. The internal 10/100 PHY implements Auto-Negotiation for twisted-pair (10T/100TX) operation by using a modified 10BASE-T link integrity test pulse sequence as defined in the IEEE 802.3u specification. The Auto-Negotiation function automatically configures the controller to operate at the maximum performance level supported across the network link. The Am79C975 controller also implements a Serial Management Interface in addition to the advanced management features offered with the Am79C973 controller. The Serial Management Interface is based on the industry standard Inter-IC (I2C) and System Management Bus (SMBus) specifications and enables a system to communicate with another network station for remote monitoring and alerting of local system management parameters and events. This simple yet powerful Serial Management Interface is capable of communicating within the system and over the network during normal operation or in low-power modes, even if the device is not initialized or set up for transmit or receive operation by the network software driver.

• Single-chip PCI-to-Wire Fast Ethernet controller
  • 32-bit glueless PCI host interface
  • Supports PCI clock frequency from DC to 33 MHz independent of network clock
  • Supports network operation with PCI clock from 15 MHz to 33 MHz
  • High performance bus mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization
  • PCI specification revision 2.2 compliant
  • Supports PCI Subsystem/Subvendor ID/ Vendor ID programming through the EEPROM interface
  • Supports both PCI 5.0 V and 3.3 V signaling environments
  • Plug and Play compatible
  • Big endian and little endian byte alignments supported
• Fully Integrated 10/100 Mbps Physical Layer Interface (PHY)
  • Conforms to IEEE 802.3 standard for 10BASE-T, 100BASE-TX, and 100BASE-FX interfaces
  • Integrated 10BASE-T transceiver with onchip filtering
  • Fully integrated MLT-3 encoder/decoder for 100BASE-TX
  • Provides a PECL interface for 100BASE-FX fiber implementations
  • Full-duplex capability for 10BASE-T and 100BASE-TX
  • IEEE 802.3u Auto-Negotiation between 10 Mbps and 100 Mbps, half- and full-duplex operation
• Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards
• Supports PC98/PC99 and Wired for Management baseline specifications
  • Full OnNow support including pattern matching and link status wake-up events
  • Implements AMDs patented Magic Packet technology for remote wake-up & power-on
  • Magic Packet mode and the physical address loaded from EEPROM at power up without requiring PCI clock
  • Supports PCI Bus Power Management Interface Specification Revision 1.1
  • Supports Advanced Configuration and Power Interface (ACPI) Specification Version 1.0
  • Supports Network Device Class Power Management Specification Version 1.0a
• Serial Management Interface enables remote alerting of system management events
  • Inter-IC (I2C) compliant electrical interface
  • System Management Bus (SMBus) compliant signaling interface and register access protocol
• Large independent internal TX and RX FIFOs
  • Programmable FIFO watermarks for both TX and RX operations
  • RX frame queuing for high latency PCI bus host operation
  • Programmable allocation of buffer space between RX and TX queues
• EEPROM interface supports jumperless design and provides through-chip programming
  • Supports extensive programmability of device operation through EEPROM mapping
• Supports up to 1 megabyte (Mbyte) optional Boot PROM and Flash for diskless node application
• Extensive programmable internal/external loopback capabilities
• Extensive programmable LED status support
• Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame
• Includes Programmable Inter Packet Gap (IPG) to address less network aggressive MAC controllers
• Offers the Modified Back-Off algorithm to address the Ethernet Capture Effect
• IEEE 1149.1-compliant JTAG Boundary Scan test access port interface and NAND tree test mode for board-level production connectivity test
• Compatible with the existing PCnet Family driver/diagnostic software
• Software compatible with AMD PCnet Family and LANCE/C-LANCE register and descriptor architecture
• Available in 160-pin PQFP and 176-pin TQFP packages
• Advanced +3.3 V CMOS process technology for low power operation