Octal D Flip-Flop with Clock Enable

The IDT74FCT377T is an octal D flip-flop built using an advanced dual metal CMOS technology. The IDT74FCT377T has eight edge-triggered, D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is low. The register is fully edge-triggered. The state of each D input, one set-up time before the low-to-high clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the low-to-high transition for predictable operation.

• A, C, and D grades
• Low input and output leakage =1µA (max.)
• CMOS power levels
• True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in SOIC and QSOP packages