Multiplier and Zero Delay Buffer

The ICS570 is a high-performance Zero Delay Buffer (ZDB)which integrates IDT’s proprietary analog/digital PhaseLocked Loop (PLL) techniques. The A version isrecommended for 5 V designs and the B version for3.3 V designs. The chip is part of IDT’s ClockBlocksTMfamily, and was designed as a performance upgrade tomeet today’s higher speed and lower voltage requirements.The zero delay feature means that the rising edge of theinput clock aligns with the rising edges of both outputclocks, giving the appearance of no delay through thedevice. There are two outputs on the chip, one being alow-skew divide by two of the other output. The deviceincorporates an all-chip power down/tri-state mode thatstops the internal PLL and puts both outputs into a highimpedance state.

• 8-pin SOIC package
• Available in Pb (lead) free package
• Pin-for-pin replacement and upgrade to ICS570M
• Functional equivalent to AV9170 (not a pin-for-pin replacement)
• Low input to output skew of 300 ps max (>60 MHz outputs)
• Ability to choose between 14 different multipliers from 0.5x to 32x
• Output clock frequency up to 170 MHz at 3.3 V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Power Down and Tri-State Mode
• Passes spread spectrum clock modulation
• Full CMOS clock swings with 25 mA drive capability at TTL levels
• Advanced, low power CMOS process
• ICS570B has an operating voltage of 3.3 V (±5%)
• ICS570A has an operating voltage of 5.0 V (±5%)
• Industrial temperature version available