Multiplexer/Latch 1-Element ECL 12-IN 28-Pin PLCC Rail

The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.The 100 Series contains temperature compensation.

• 850ps Max. LEN to Output
• 825ps Max. D to Output
• Single-Ended Outputs
• Asynchronous Master Reset
• Dual Latch-Enables
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V with V_EE = -4.2 V to -5.7 V
• Internal Input Pulldown Resistors
• ESD Protection: > 2 kV HBM, > 200 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
  For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
• Transistor Count = 239 devices
• Pb-Free Packages are Available