Multilevel Input to Differential LVPECL/LVNEC Clock or Data Receiver/Driver/Translator Buffer 8-Pin SOIC N Rail

The NB6L16 is a high precision, low power ECL differential clock or data receiver/driver/translator buffer. The device is functionally equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With output transition times of 70 ps, it is ideally suited for high frequency, low power systems. The device is targeted for Backplane buffering, GbE clock/data distribution, Fibre Channel distribution and SONET clock/data distribution applications.Input accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV ECL signals.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

• Input Clock Frequency6 GHz
• Input Data Rate Frequency6 Gb/s
• Low 12 mA Typical Power Supply Current
• 70 ps Typical Rise/Fall Times
• 130 ps Input Propagation Delay
• On-Chip Reference for ECL Single-Ended Input - V_BB Output
• PECL Mode Operating Range: V_CC = 2.375 V to 3.465 V with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 with V_EE = 2.375 V to 3.465 V
• Open Input Default State
• LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input Compatible
• Low-power Clock Buffering for Power constrained PC Add-on cards