Multichannel Network Controller IC, 388-Pin BGA

The MUNICH256 is a highly integrated protocol controller that implements HDLC, PPP and transparent (TMA) protocol processing for 256 channels. An on-chip data management unit is optimized to transfer data packets via a PCI interface by minimizing the bus load. The serial interface of the device can be configured in a 16-port mode and additionally in a 28-port mode. The 16-port mode provides a clock pin, a data pin and a frame synchronization pin for each port and direction. The 28-port mode provides a clock pin and a data pin per port and direction. In this mode frame boundaries are indicated by clock gaps. Table 1-1 below shows the pin configuration and the supported frame structures in the 16-port mode and the 28-port mode.

• Configurable port interface which operates in 16-port mode or 28-port mode.
• In 16-port mode protocol processing on up to 16 T1, E1, channelized 4 MBit/s, channelized 8 MBit/s or unchannelized links for frame relay, router or DSLAM applications with a maximum aggregate data rate of up to 90 Mbit/s per direction at 66 MHz PCI frequency
• In 28-port mode protocol processing on up to 28 T1, E1 or unchannelized links. T1, E1 frame boundaries are indicated by clock gaps
• Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum of 16 links, for HDLC, PPP or transparent mode (TMA) processing
• Concatenation of any, not necessarily consecutive, time slots to logical channels on each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels
• Additional support of unchannelized modes, with data rates of up to 45 Mbit/s on port zero and 8.192 Mbit/s on all other ports
• Provides 32kB data buffer in transmit direction and 12kB data buffer in receive direction
• Independently selectable pay load loops for each port
• Provides a test function which allows to switch one out of 16 (28) ports to a test port
• System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM interface
• Integrates a local microprocessor master and slave interface (demultiplexed 16 bit address and data bus in Intel mode or Motorola mode) which allows access to the local bus via the PCI bus or which can communicate with a PCI host processor through an on-chip mailbox
• JTAG boundary scan according to IEEE1149.1 (5 pins)
• 0.25 µm, 2.5V core technology
• I/Os are 3.3V tolerant and have 3.3V driving capability
• Package P-BGA 388 (35mm x 35mm, pitch 1.27mm)
• Full scan path and BIST of on-chip RAMs for production test
• Performance: 90 Mbit/s data throughput per direction at 66 MHz
• Estimated power consumption: 3W at 66 MHz
• Also available as device with extended temperature range -40 to +85°C