Multi Function Gate 2-Element 2-IN CMOS 8-Pin VSSOP

The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A x C. The output 2Y provides the Boolean function: 2Y = A x B + A x C. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire Vcc range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire Vcc range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
  • JESD8-12 (0.8 V to 1.3 V)
  • JESD8-11 (0.9 V to 1.65 V)
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-B (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114F Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V
• Low static power consumption; Icc = 0.9 µA (maximum)
• Latch-up performance exceeds 100 mA per JESD78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of Vcc
• Ioff circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C