MIXED SIGNAL MOBILE EMBEDDED CONTROLLER WITH FLASH AND ARC C

The MEC1633 is the mixed signal base component of a multi-device advanced I/O controller architecture. The MEC1633 incorporates a high-performance 32-bit ARC 625D embedded microcontroller with a 192 Kilobyte Embedded Flash Subsystem, 16 Kilobytes of SRAM, 1 Kilobyte EEPROM emulation, and a 2 Kilobyte EEPROM. The MEC1633 communicates with the system host using the Intel Low Pin Count bus.The MEC1633 is the EC Base Component of a split-architecture Advanced I/O Controller system which uses BC-Link communication protocol to access up to three companion components. The BC-Link protocol is peer-to-peer providing communication between the MEC1633 embedded controller and registers located in a companion.The MEC1633 is directly powered by two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (Vcc) to provide “instant on” and system power management functions. The MEC1633 also contains an integrated VTR Reset Interface and a system Power Management Interface that supports low-power states and can drive state changes as a result of hardware wake events as defined by the MEC1633 Wake Interface.The MEC1633 defines a software development system interface that includes an MCU serial Debug Port, a two pin serial debug port with a 16C550A register interface that is accessible to the EC or to the LPC host and can operate up to 2 MB/s, a flexible Flash programming interface, a Port 80 BIOS Debug Port, Gang Programmer Interface, and a JTAG interface. The EC can also drive the JTAG interface as a master.

• 3.3V Operation
• ACPI Compliant
• LPC Interface
  • Supports LPC Bus frequencies of 19.2MHz to 33MHz
• VTR (standby) and VBAT Power Planes
  • Low Standby Current in Sleep Mode
• Configuration Register Set
  • Compatible with ISA Plug-and-Play Standard
  • EC-Programmable Base Address
• ARC-625D Embedded Controller (EC)
  • 16 KB Single Cycle 32-bit Wide Dual-ported SRAM, Accessible as Closely Coupled Data Memory and Instruction Memory
  • 4KB Boot ROM
  • 32 x 32 -> 64 Fast Multiply
  • Divide Assist and Saturation Arithmetic
  • Maskable Interrupt Aggregator/Accelerator Interface
  • Maskable Hardware Wake-Up Events
  • Sleep mode
  • JTAG Debug Port, Includes JTAG Master
  • MCU Serial Debug Port
  • 1µS Delay Register
  • 10-Channel DMA Interface Supports SMBus Controllers and EC/Host GP-SPI Controllers