Memory System 80-Pin TQFP

The PSD family of memory systems for microcontrollers (MCUs) brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP).

• Flash in-system programmable (ISP) peripheral for 8-bit MCUs
• Dual bank flash memories
  • 4 Mbits of primary Flash memory (8 uniform sectors, 64 Kbytes)
  • 256 Kbits of secondary Flash memory with 4 sectors
  • Concurrent operation: READ from one memory while erasing and writing the other
• 64 Kbit of SRAM
• 52 reconfigurable I/O ports
• Enhanced JTAG serial port
• PLD with macrocells
  • Over 3000 gates of PLD: CPLD and DPLD
  • CPLD with 16 output macrocells (OMCs) and 24 Rev 5 macrocells (IMCs)
  • DPLD - user defined internal chip select decoding
• 52 individually configurable I/O port pins They can be used for the following functions:
  • MCU I/Os
  • PLD I/Os
  • Latched MCU address output
  • Special function I/Os.
  • I/O ports may be configured as open-drain outputs.
• In-system programming (ISP) with JTAG
  • Built-in JTAG compliant serial port allows full-chip in-system programmability
  • Efficient manufacturing allow easy product testing and programming
  • Use low cost FlashLINK cable with PC
• Page register
  • Internal page register that can be used to expand the microcontroller address space by a factor of 256
• Programmable power management
• High endurance
  • 100,000 Erase/WRITE cycles of Flash memory
  • 1,000 Erase/Write cycles of PLD
  • 15 year data retention
• 5 V±10% single supply voltage
• Standby current as low as 50 µA
• Memory speed
  • 70 ns Flash memory and SRAM access time for VCC = 4.5 to 5.5 V
  • 90 ns Flash memory and SRAM access time for VCC = 4.5 to 5.5 V
• ECOPACK® package