MASS STORAGE WITH 128GB DENSITY

Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#). This Micron NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organization.

• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Single-level cell (SLC) technology
• Organization
  • Page size x8: 8640 bytes (8192 + 448 bytes)
  • Block size: 128 pages (1024K + 56K bytes)
  • Plane size: 2 planes x 2048 blocks per plane
  • Device size: 32Gb: 4096 blocks;
  • 64Gb: 8192 blocks;
  • 128Gb: 16,384 blocks;
  • 256Gb: 32,786 blocks
• Synchronous I/O performance
  • Up to synchronous timing mode 5
  • Clock rate: 10ns (DDR)
  • Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
  • Up to asynchronous timing mode 5
  • tRC/tWC: 20ns (MIN)
  • Read/write throughput per pin: 50 MT/s
• Array performance
  • Read page: 35µs (MAX)
  • Program page: 350µs (TYP)
  • Erase block: 1.5ms (TYP)
• Operating Voltage Range
  • VCC: 2.7–3.6V
  • VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
  • Program cache
  • Read cache sequential
  • Read cache random
  • One-time programmable (OTP) mode
  • Multi-plane commands
  • Multi-LUN operations
  • Read unique ID
  • Copy back
• First block (block address 00h) is valid when shipped from factory. For minimum required ECC, see Error Management
• RESET (FFh) required as first command after power-on
• Operation status byte provides software method for detecting
  • Operation completion
  • Pass/fail condition
  • Write-protect status
• Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the synchronous interface
• Copy back operations supported within the plane from which data is read
• Quality and reliability
  • Data retention: JESD47G compliant; see qualification report
  • Endurance: 60,000 PROGRAM/ERASE cycles
• Operating temperature:
  • Commercial: 0°C to +70°C
  • Industrial (IT): –40ºC to +85ºC
• Package
  • 52-pad LGA
  • 48-pin TSOP
  • 100-ball BGA
  • 132-ball BGA