LVDS Receiver 16-Pin TSSOP T/R

The STLVDS32 is a differential line receiver that implements the electricalcharacteristics of low voltage differential signaling (LVDS). This signaling techniquelowers the output voltage levels of 5 V differential standard levels (such asTIA/EIA-422B) to reduce the power, increase the switching speeds and allow operationswith a 3.3 V supply rail. This differential receiver provides a valid logical outputstate with a 3.3 V supply rail. It also provides a valid logical output state with a±100 mV differential input voltage within the input common mode voltage range. The inputcommon mode voltage allows 1 V of ground potential difference between two LVDS nodes.The intended application of this device and signalling technique is both point-to-pointand multidrop data transmission over controlled impedance media approximately 100 O. Thetransmission media may be printed circuit board traces, backplanes or cables. Theultimate rate and distance of data transfer depend upon the attenuation characteristicsof the media and noise coupling to the environment.The STLVDS32 version is characterized for operation from -55 C to °125 C.

Meets or exceeds the requirements of ansi TIA/EIA-644 standard

Operates with a single 3.3 V supply

Designed for signaling rate up to 400 Mbps

Differential input thresholds ±100 mV max

Typical propagation delay time of 2.5 ns

Power dissipation 60 mW typical per receiver at 200 MHz

Low voltage TTL (LVTTL) logic output levels

Pin compatible with the AM26LS32, SN65LVD32

Open circuit fail safe

ESD protection:

7 kV receiver pins

3 kV all pins vs gnd