Latch Transparent 6-CH D-Type 28-Pin PLCC Rail
The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.The 100 Series contains temperature compensation.
- 800ps Max. Propagation Delay
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors
- ESD Protection: > 1 kV HBM, > 75 V MM
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D - Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
- Transistor Count = 173 devices
- Pb-Free Packages are Available
Характеристики
| Бренд | ON Semiconductor |
|---|---|
| Maximum P | 0.55@5V ns |
| Type Prod | D-Type |
| Number Of | 6 |
| Рабочая температура | 0 to 85 °C |
| Maximum O | -5.7|5.7 V |
| Maximum L | 50 mA |
| Lead Finish | Matte Tin |
| Polarity | Inverting/Non-Inverting |
| Max Proce | 260|265 |
| Bus Hold | Нет |
| Number Of | 2 |
| Latch Mode | Transparent |
| Typical O | -5|5 V |
| Number Of | 6 |
| Number Of | 6 |
| Number Of | 1 |
| Minimum O | -4.2|4.2 V |
| Supplier | PLCC |
| Msl Level | 3 |
| Set Reset | Master Reset |
| Maximum H | -50 mA |
| Описание продукта | 11.58 x 11.58 x 3.69 mm |
| Schedule B | 8542390000 |
| HTSN | 8542390001 |
| Страна происхождения | United States |
SKU: MC100E150FNG