IP Module - Core1553BRM License

Microsemi Core1553BRM provides a complete MIL-STD-1553B bus controller (BC), remote terminal (RT), or bus monitor terminal (BM or MT). Core1553BRM can be configured to provide all three 1553 functions or any combination thereof. The core is supported in all recent Microsemi Flash, antifuse, and radiation-tolerant product families

• Indexing
  • The core, when configured as an RT, can support bulk data transfer, buffering up to 256 messages per subaddress. Once a specified number of messages has been received, the core can signal the host subsystem via an interrupt.
• Buffer Ping Pong
  • The core supports the use of dual buffers per subaddress for data processing. This allows the core to process messages using the primary buffer while the host or subsystem can access the secondary buffer to store new data for transmission or process previously received data. The core will switch back and forth (ping pong) between the two buffers when a message is received or transmitted.
• Circular Buffers
  • To simplify the software servicing of the RTs during periodic or bulk data transfers, the core supports the use of circular buffers. The user can select between two circular buffer modes at start-up or rely on the default operation.
• Broadcast
  • The core architecture allows the user to choose whether or not data received from broadcast commands is to be segregated from data received from non-broadcast commands.
• Interrupt History
  • The core architecture supports a programmable interrupt structure that can store up to 16 interrupts, and the subaddress or command block that generated each interrupt, in a 32-word buffer before servicing.
• Message Information
  • Along with message data words, the core also writes a Message Information Word (MIW) and Time Tag for each processed message. The MIW contains information on the type of message transacted, the word count, and any message errors.