Highly functional 32-bit microcontroller with color LCD controller, capable of operating at 80 MHz

The TMP92CZ26A is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. The TMP92CZ26AXBG is housed in a 228-pin BGA package.

• CPU: 32-bit CPU (High-speed 900/H1 CPU)
  • Compatible with TLCS-900/L1 instruction code
  • 16 Mbytes of linear address space
  • General-purpose register and register banks
  • Micro DMA: 8channels (62.5 ns/4 bytes at fSYS = 80 MHz, best case)
• Minimum instruction execution time: 12.5 ns (at fSYS = 80 MHz)
• Internal RAM: 288 Kbytes (can be used for program, data and display memory)
  • Internal ROM: 8 Kbytes (memory for Boot only)
  • Possible downloading of user program through either USB, UART.
• External memory expansion
  • Expandable up to 3.1 Gbytes (shared program/data area)
  • Can simultaneously support 8-and 16-bit width external data buses Dynamic data bus sizing
  • Separate bus system
• Memory controller
  • Chip select output: 4 channels
  • One channel in 4 channels is enabled detailed AC enable setting
• 8-bit timers: 8 channels
• 16-bit timer/event counter: 2 channels
• General-purpose serial interface: 1 channel
  • UART/synchronous mode
  • IrDA ver.1.0 (115.2 kbps) selectable(There is the restriction in the setting baud rate when use this function togetherother functions)
• Serial bus interface: 1 channel
  • I²C bus mode only
• USB (universal serial bus) controller: 1 channel
  • Supports USB (ver.1.1)
  • Full-speed (12 Mbps) (Low-speed is not supported.)
  • Endpoint 0: Control 64 bytes × 1 FIFO
  • Endpoint 1: BULK (output) 64 bytes × 2 FIFOs
  • Endpoint 2: BULK (input) 64 bytes × 2 FIFOs
  • Endpoint 3: Interrupt (input) 8 bytes × 1 FIFO
  • Descriptor RAM: 384 bytes
• I2S (Inter-IC Sound)interface: 2 channels
  • I2S bus mode selectable (Master, transmission only)
  • Data Format is supported Left/Right Justify
  • 128-byte FIFO buffer (64 bytes × 2) per channel
• LCD controller
  • Supports monochrome, 4, 16 and 64 gray levels and 256/4096/65536 colors for STN
  • Supports 4096/65536/262144/16777216 colors for TFT
  • Supports PIP (Picture In Picture Display)
  • Supports H/W Rotation function for support to various LCDM
• SDRAM controller: 1 channel
  • Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate)SDRAM
  • Possible to execute instruction on SDRAM
• Timer for real-time clock (RTC)
  • Based on TC8521A