HDLC Controller 28-Pin PLCC T/R

The MT8952B HDLC Protocol Controller frames and formats data packets according to X.25 (Level 2) Recommendations from the CCITT. The MT8952B HDLC Protocol Controller handles bit oriented protocol structure and formats the data as per the packet switching protocol defined in the X.25 (Level 2) recommendations of the CCITT. It transmits and receives the packeted data (information or control) serially in a format shown in Figure 3, while providing the data transparency by zero insertion and deletion. It generates and detects the flags, various link channel states and the abort sequence. Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial. In addition, it can generate and detect a Go Ahead sequence and recognize a single byte address in the received frame. There is also a provision to disable the protocol functions and provide transparent access to the serial bus through the parallel port.

• Formats data as per X.25 (CCITT) level-2 standards
• Go-Ahead sequence generation and detection
• Single byte address recognition
• Microprocessor port and directly accessible registers for flexible operation and control
• 19 byte FIFO in both send and receive paths
• Handshake signals for multiplexing data links
• High speed serially clocked output (2.5 Mbps)
• ST-BUS compatibility with programmable channel selection for data and separate timeslot for control information
• Independent watchdog timer
• Facility to disable protocol functions
• Low power ISO-CMOS technology