Flip Flop JK-Type Neg-Edge 2-Element 14-Pin SOIC T/R

The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.

Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times

Asynchronous Reset

Complementary Outputs

Buffered Inputs

Typical f_MAX = 60MHz at V_CC = 5V, C_L = 15pF, T_A = 25°C

Fanout (Over Temperature Range)

• Standard Outputs . . . . .10 LSTTL Loads
• Bus Driver Outputs . . . . . .15 LSTTL Loads

Wide Operating Temperature Range . . . –55°C to 125°C

Balanced Propagation Delay and Transition Times

Significant Power Reduction Compared to LSTTL Logic ICs

HC Types

• 2V to 6V Operation
• High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

HCT Types

• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
• CMOS Input Compatibility, I_l = 1µA at V_OL, V_OH