Flip Flop D-Type Pos-Edge 2-Element 8-Pin SSOP T/R

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Available in the Texas Instruments NanoFree Package

Supports 5-V V_CC Operation

Inputs Accept Voltages to 5.5 V

Max t_pd of 4.2 ns at 3.3 V

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C

Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C

I_off Feature Supports Live Insertion, Partial-Power-Down Mode Operation and Back Drive Protection

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

ESD Protection Exceeds JESD 22

• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)