Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOP T/R
The 74VHC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUTS during the positive going transition of the clock pulse. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
- HIGH SPEED: fMAX = 170 MHz (TYP.) at Vcc = 5V
- LOW POWER DISSIPATION: Icc = 2 µA (MAX.) at TA=25°C
- HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
- POWER DOWN PROTECTION ON INPUTS
- SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)
- BALANCED PROPAGATION DELAYS: tPLH ? tPHL
- OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
- PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74
- IMPROVED LATCH-UP IMMUNITY
Характеристики
| Бренд | STMicroelectronics |
|---|---|
| Описание продукта | 8.75 x 4 x 1.65 mm |
| Maximum H | -8 mA |
| Bus Hold | Нет |
| Polarity | Inverting/Non-Inverting |
| Set Reset | Set/Reset |
| Number Of | 1 |
| Number Of | 2 |
| Triggering Type | Positive-Edge |
| Рабочая температура | -55 to 125 °C |
| Input Sig | Single-Ended |
| Maximum L | 8 mA |
| Number Of | 2 |
| Maximum P | 15.4@3.3V|9.3@5V ns |
| Maximum O | 5.5 V |
| Maximum Q | 0.002 mA |
| Output Si | Differential |
| Logic Function | D-Type |
| Number Of | 1 |
| Propagati | 50 pF |
| Minimum O | 2 V |
| Lead Finish | Tin |
| Supplier | SOP |
| Max Proce | 260|300 |
| Typical O | 2.5|3.3|5 V |
| Msl Level | 1 |
| Schedule B | 8542390000 |
| HTSN | 8542390001 |
SKU: 74VHC74MTR